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subversion! Intel plots Big.Little size x86 new architecture: Codename Lakefield

via:博客园     time:2018/4/7 19:01:04     readed:748

Some friends who know something about the mobile SoC will certainly be familiar with the "Big. Little" architecture. This is a heterogeneous CPU design that was first introduced on the ARM platform and can take into account both high performance and low power consumption.

Have you ever thought that Intel x86 can follow suit?

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In theory, Intel has developed many CPU architectures based on the x86 instruction set. High-performance cores such as "Coffee Lake", "Skylake", "Haswell", etc., low-power platforms have ATOM in use. “Silvermont”“Goldmont”etc.

According to the Motley Fool technology broke the people Ashraf Eassa, Intel is secretly developing the code design "Lakefield" architecture design, in which the high-performance nuclear power is based on "Icelake", based on "small" Tremont&rdquo.

IceLake is the platform code behind Cannonlake and is said to be used on the 10th generation Core, while Tremont is the successor to Goldmont Plus.

Eassa revealed that Intel will build "Lakefield" SoC products with thermal design power consumption of 28W and 35W for products such as 2-in-1 notebooks.

Of course, for such a brand-new "small-core" design, it may be necessary to do some in-depth optimization work on compatibility so that operating systems, software, games, etc. can be fully identified and efficiently mobilized.

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