Machine Heart report
With the end of Moore's law, people have been exploring a new direction of chip development, one of which is to replace silicon with carbon nanotubes. However, due to high purity and process requirements, carbon nanotubes can not be used to make chip processors. But recently, the MIT team has proposed a new carbon nanotube chip manufacturing technology, which can reduce the purity requirement by four orders of magnitude, and the carbon nanotube chip can run the Hello World program.
After years of efforts, MIT researchers overcome many challenges in chip design and manufacturing, and constructed a modern microprocessor using carbon nanotubes. This microprocessor is faster and more energy efficient than traditional silicon chips.
The research has recently been published in Nature, which can use traditional silicon chip manufacturing process, representing the direction of carbon nanotube microprocessors towards more practical.
Note: Carbon nanotube wafers, 32 chips per wafer.
Silicon transistors have been operating in the computer industry for decades. They are key microprocessor components that switch between 1 and 0, which represents computing power. As predicted by Moore's Law, the industry can reduce the size of transistors every few years and integrate more transistors into chips to meet the growing computing needs. But many experts predict that transistors will stop shrinking and become increasingly inefficient.
Manufacturing carbon nanotube field effect transistors (CNFETs) has become the main goal of the next generation of computers. The results show that compared with silicon, CNFET can increase energy efficiency by about 10 times and speed up. However, when large-scale production, carbon transistors often have many performance impacts, so it is still difficult to use in reality.
The carbon NanoChip designed by MIT is a 16-bit microprocessor with 14,000 CNFETs. To some extent, it overcomes the above shortcomings and can accomplish the same tasks as commercial microprocessors. Their paper, published in Nature, explains the design of the microprocessor in detail, and contains more than 70 pages of manufacturing details.
The microprocessor is mainly based on RISC-V open source chip architecture, which has a set of instructions that microprocessors can execute. The microprocessor constructed by the researchers can execute the whole set of instructions accurately, and also try to execute the classic "Hello World!" program, i.e., print out "Hello, World!" I am RV16XNano, made from CNTs.
Figure 1: A schematic diagram of RV16X-NANO, in which a is an image of the RV16X-NANO chip, and B is a three-dimensional physical layout of the RV16X-NANO scaled rendering.
Since the purity can not be reached, it is better to try to reduce the influence of impurities.
The microprocessor is based on the previous version designed six years ago by Shulaker and other researchers, which has only 178 CNFETs running on a single data bit. Since then, Shulaker and his MIT colleagues have tackled three major challenges facing the production of the processor: material defects, process defects and functional problems.
For many years, the inherent defects of carbon nanotubes have been a major "curse" in this field, Shulaker said. Ideally, CNFET requires semiconductor properties to achieve conductive switches. But inevitably, there will always be some impurities in the material, that is, a small part of carbon nanotubes are metallic, which will slow down or prevent the conductivity switch of nanotubes. In order to overcome these problems, the purity of carbon nanotubes should reach 99.9999%, which is almost impossible to achieve today.
Since the purity is difficult to achieve, researchers have found a new way to think about how to weaken or eliminate the impact of these metallic carbon nanotubes. They proposed a technology called DREAM (design resiliency against metallic CNTs), which somehow treats metallic carbon nanotubes to eliminate their impact on calculations. Using this technology, they reduced the purity requirement of carbon nanowafers by four orders of magnitude (10,000 times), that is to say, only 99.99% purity can be achieved, which can be achieved by current technology.
Design circuits require libraries of different logic gates connected to transistors that can be combined to create adders and multipliers, just as letters are combined into words. Researchers have found that these metallic carbon nanotubes have different effects on different pairs of these gates.
For example, a metallic carbon nanotube in gate A may destroy the connection between A and B. However, several metallic carbon nanotubes in gate B may have no effect on the above connection. In chip design, there are many ways to use code to simulate circuits. Researchers simulated different combinations of gates for robustness/robustness to all metallic carbon nanotubes. Then they customized a chip design program to automatically learn how to minimize the impact of metal carbon nanotubes. When designing a chip, the program only needs to make use of those robust combinations.
The manufacturing process of CNFET is as follows: Firstly, carbon nanotubes in solution are placed on pre-designed wafers. However, some carbon nanotubes inevitably gather randomly to form a huge mass, like a mass of spaghetti, which can lead to chip contamination.
To clean up the contamination, researchers have developed a method called RINSE, which removes carbon nanotubes by selective stripping. Before carbon nanotubes are placed on the wafer, the wafer is pretreated and coated with a reagent to enhance the adhesion ability of carbon nanotubes. The wafer is then coated with a specific polymer and immersed in a solvent. This solvent can wash away the polymer and only take away the large lumps. Single carbon nanotubes were not affected. Compared with similar methods, this technology can reduce the particle density on the chip by 250 times.
Note: Five-layer chip manufacturing process.
Finally, the researchers solved the common functional problems on CNFET. Binary computing requires two kinds of transistors: "N" turns on when 1 bit passes, and "P" turns off when 0 bit passes; and "P" turns on the opposite. Generally speaking, the fabrication of these two carbon nanotubes is challenging, and the transistor performance is good or bad. To solve this problem, researchers have developed a technology called MIXED, i.e. "Metal Surface Engineering and Electrostatic Doping Crossing", which can accurately adjust and optimize the functions of transistors.
This technique is accomplished by attaching a specific metal, such as platinum or titanium, to each transistor, thus modifying the transistor to a P or N type. They then wrapped CNFETs in an oxide using atomic-layer deposition, enabling them to adjust the characteristics of transistors for specific applications. For example, the transistors needed on the server must be fast and of course very energy-intensive. But on wearable or medical implantable devices, transistors with slow running speed and low power consumption are needed.
The main goal of this approach is to enable chips to be used in real applications. To this end, researchers have now begun to apply these manufacturing processes to silicon chip manufacturers. The study was funded by the Defense Advanced Research Projects Agency (DARPA). Although no one can tell when carbon nanochips will be on the market, Shulaker says that could happen in five years.
"We feel that this is no longer a question of impossibility, but of when it will be achieved. "He said.
Co-author Max M. Shulaker said: "This is by far the most advanced chip, which utilizes emerging nanotechnology and has excellent performance in performance and energy consumption. Silicon is limited. Carbon nanotubes are the most promising way to overcome the limitations of silicon materials if we want to continue to make progress in computing. This Nature paper completely changed our technology of using carbon nanotubes to make chips. "Launch a final impact on Moore's lawOn the way of upgrading the process, the new technology has been difficult, and the use of new chip materials may be the right direction of development in the future. A few days ago, the company made a similar point at the HotChips conference.
"There is no doubt that Moore's law is still valid and in good condition. It has not died, slowed down or become ill. Philip Wong, head of research and development at TSMC and vice president of technology research, said in a keynote speech at the HotChips conference.
TSMC believes that new directions such as carbon nanotubes (1.2nm scale) and two-dimensional layered materials can make transistors faster and smaller in size. Meanwhile, phase change memory (PRAM) and rotating moment transfer random access memory (STT-RAM) will be packaged directly with processors and reduced. Volume, speed up data transfer; in addition, there are three-dimensional stack packaging technology. TSMC even predicts that in 2050, transistors will enter the hydrogen atom scale, i.e. 0.1 nm.