AMD will officially release the third-generation Xiaolong 7003 series data center processor code named "Milan" this month, which is based on 7Nm technology and zen3 architecture, with 64 core 128 threads at most, and supports eight channels of ddr4-3200 memory and 128 channels of PCI 4.0. In the future, it will be5nm technology, zen4 architecture, code named "Genoa" (Genoa), the product sequence should be the fourth generation Xiaolong 7004 series.
It's just that the release time may have to be patient and so on. It's expected that it will be in the second half of 2021 or even early 2022 at the earliest.
Now, twitter blogger @ executablefix has exposed four generations of core specifications for the first time:
1. The maximum number of cores is 96, and the maximum number of threads is 196, which is half of the current number.
The internal structure is still chiplet, with 8 cores per chip12And continue with an IO chip.
2. The memory supports a new generation of ddr5 with a maximum frequency of 5200mhz and a half increase in the number of channels to 12.
If there are 2 memories per channel, the maximum number of single channel is 24. If 128GB memory is used, the maximum number of single channel is 24Up to 3TBMemory.
3. The I / O supports the new generation of pcie5.0. There are up to 128 channels in a single channel, but 160 channels in a dual channel.
This means that the number of channels required for internal communication between the two channels has been reduced from 128 to 96. After all, the bandwidth has doubled.
4. Thermal design power consumption up to 320W, 40W more than now, while supporting up to 400W (CTDP).
5. For the first time, the interface is replaced with the new SP5 lga6096, which has up to 2002 contacts more than the current SP3 lga4094.
After all, we need to support ddr5 and PCI 5.0, but interestingly, the name of SP4 has been skipped.
Comparison of internal structure between Xiaolong of the second and third generations and Xiaolong of the fourth generation
In terms of competitive products, Intel will release the fourth generation of scalable Xeon code named sapphire rapids at the end of this year. The specification is also a leap forward, but it is inferior to the fourth generation Xiaolong in all aspects.
10nm enhanced superfin manufacturing process, golden Cove CPU architecture, MCM multi-core package, up to 4 small chips, 60 cores and 120 threads (at least 4 cores hidden in the initial stage), integrated up to 64GB hbm2e high bandwidth memory, supported up to 8-channel ddr5-4800, 80 pieces of pcie5.0, thermal design power consumption up to 400W, interface replaced with new lga4677-x.