Amd officially announced today that,At 0:00 Beijing time on March 16 (11:00 EDT on March 15 / 8:00 Pacific time on March 15), an online global conference will be held to officially launch the third generation epyc Xiaolong processor.
At that time, Dr. Su Zifeng, President and CEO of AMD, mark papermaster, executive vice president and CTO of technology and engineering, Forrest norrod, general manager and senior vice president of data center and embedded solutions division, and Dan McNamara, general manager and senior vice president of server business will all attend the conference and give speeches.
According to AMD,Compared with the competitive products, the performance of the third generation Xiaolong can be exceeded by up to 68%.
The third generation Xiaolong development code is Milan. It will continue to use TSMC's 7Nm process to manufacture, but will upgrade to the new zen3 architecture. In addition to the frequency and power consumption, other overall specifications are basically the same as the second generation. The internal design is a chiplet chip, with a maximum of 64 core 128 threads, 32MB secondary cache, 256MB tertiary cache, eight channel ddr4-3200 memory, and 128 PCI 4.0 buses.
However, with the new architecture, the performance and energy efficiency of the third generation Xiaolong will be significantly improved.
According to the previous exposure,The third generation Xiaolong will have at least 19 different modelsIt includes 15 dual channel models and 4 single channel models, with 8 / 16 / 24 / 28 / 32 / 48 / 56 / 64 cores.
Among them, the flagship model is Xiaolong 7763, the core frequency is 2.45-3.5ghz, and the thermal design power consumption is up to 280W.
There are a number of frequencies that reach or even exceed 4.0ghz. For example, the 32 core Xiaolong 75f3 has 3.25-4.0ghz, and the thermal design power consumption is 280W, while the 8-core Xiaolong 72f3 has a maximum of 3.65-4.1ghz, and the thermal design power consumption is 180W.
And then four generations of Xiaolong, code named Genoa, will upgrade 5nm technology and zen4 architecture. It is said that up to 96 core 192 threads, 12 channel ddr5-5200 memory, 128 PCI 5.0 buses, thermal design power consumption up to 320W (up to 400W), and the interface is changed to SP5 lga6096 for the first time.
For Intel, it will be released in the near futureThe first application of 10nm technology and repeated ticket skipping of the third generation can be extended to strong ice lake spIt is expected that up to 36 core 72 threads.
There will be a fourth generation of sapphire rapids next yearIt will upgrade the 10nm enhanced superfin manufacturing process, multi-core packaging up to 56 cores, 112 threads (4 hidden), 64GB HBM memory, support eight channel oddr5-4800, 80 pieces of pcie5.0, thermal design power consumption up to 400W, and the interface will also become lga4677.
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